As referred to as a memory wall problem, memory access is a bottleneck in performance and power consumption of processor cores. In order to mitigate this problem, processors having large-capacity cache memories built near a main memory have become widespread with the advancement of memory techniques as a technical background.
In large-capacity cache memories, with increase in stored data amount, tag memories require larger capacity, which store meta information, namely, address information, on data stored in the cache memories. With the increased capacity, latency of the tag memories increases. In some cases, the latency of tag memories of large-capacity cache memories becomes the same degree as the latency of upper-layer cache memories. In such a case, it cannot be disregarded that the latency of tag memories affects the overall performance of a processor system.
The present embodiment provides a cache memory system including:
cache memories of at least one layer, each cache memory having a data cache to store data and a tag section to store an address of each data stored in the data cache; and
a translation lookaside buffer to store page entry information that includes address conversion information for virtual addresses issued by a processor to physical addresses and cache presence information that indicates whether data corresponding to each converted physical address is stored in a specific cache memory of at least one layer.